A microcontroller is generally a computer-on-a-chip optimized to control electronic devices. A microcontroller typically includes a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), input/output (I/O) ports, and timers. Unlike a general-purpose computer, which also includes similar components, a microcontroller is usually designed to implement a very specific task—e.g., to control a particular system. As a result, the components of a microcontroller can be simplified and reduced, which cuts down on production costs. Several architectures exist for microcontrollers. Two architectures in particular are the Harvard architecture and the Von Neumann architecture.
FIG. 1 shows a microcontroller 100 in accordance with the Harvard architecture. Microcontroller 100 includes a CPU 102, a program memory 104, a data memory 106, an instruction bus 108, and a data bus 110. Program memory 104 stores a set of instructions to be executed by CPU 102. Data memory 108 stores the data required for the execution of the instructions, and also stores result data. The term Harvard architecture originally referred to computer architectures that used physically separate storage and signal pathways for instructions and data. Specifically, the term originated from the Harvard Mark relay-based computer, which stored instructions (e.g., computer program instruction code) on punched tape and stored data in relay latches. Accordingly, as shown in FIG. 1, program memory 104 is physically separate from data memory 106 and instruction bus 108 is physically separate from data bus 110. In a microcontroller in accordance with the Harvard architecture, the CPU (e.g., CPU 102) can read (or fetch) an instruction and read/write data at the same time. Consequently, such a microcontroller is generally fast as the microcontroller can fetch a next instruction at the same time a current instruction is being executed.
In contrast to the Harvard architecture, FIG. 2 shows a microcontroller 200 in accordance with the Von Neumann architecture. The Von Neumann architecture is a model for a computing machine that uses a single structure (memory) to store both the set of instructions to be executed as well as the data required for (and generated from) execution of the set of instructions. Accordingly, microcontroller 200 includes a CPU 202, a combined program and data memory 204, and a single instruction/data bus 206. In a microcontroller with a Von Neumann architecture, the CPU can either fetch an instruction or read/write data to the memory, however, both cannot occur at the same time since the instructions and data use the same signal pathway (or bus) and memory. By treating the instructions in the same way as the data, a microcontroller in accordance with the Von Neumann architecture (e.g., microcontroller 200) can easily change the stored instructions (e.g., to modify or increment an address portion of the stored instructions). In other words, the microcontroller is re-programmable.
Typically, in application-specific integrated circuits (ASICs) that use an embedded microcontroller having either only a program memory and a data memory (e.g., in accordance with the Harvard architecture) or only a single combined program and data memory (e.g., in accordance with the Von Neumann architecture), modifying the instructions (e.g., for testing and debugging purposes) within the program memory or the combined program and data memory (each of which is typically a read-only memory (ROM)) is generally a difficult task. For example, if a programmer desires to modify the instructions within the ROM memory, the ASIC including the embedded microcontroller must typically be re-spun in order to change the instructions placed in the ROM memory. Consequently, the design cycle and time to market of the ASIC are affected due to the turn around time needed to re-spin the ASIC. Also, it is generally expensive to re-spin an ASIC, especially when state of the art masks are used in the re-spin process.
A conventional technique to address the problem of modifying instructions within a ROM memory includes providing an extra RAM memory with external access within a microcontroller, such as microcontroller 300 shown in FIG. 3. Microcontroller 300 includes a CPU 302, a program memory 304, a data memory 306, an instruction bus 310 and a data bus 312. Microcontroller 300 further includes an extra RAM memory 308 in communication with CPU 302 through instruction bus 310. Extra RAM memory 308 is typically used only for debugging purposes and can be re-programmed (through the external access) and be used as a complement of the existing program memory 304. One disadvantage of including an extra RAM memory within a microcontroller design is that the extra RAM memory generally takes up valuable die space or silicon real estate. Once instruction code within a ROM has been finalized, an ASIC typically goes into production having the extra RAM memory still occupying the (expensive) silicon real estate, and because the extra RAM memory is generally only used for testing and debugging purposes, the extra RAM memory is typically goes unused during normal operation of the ASIC. As production quantities of ASICs increase, cumulatively, the extra area taken up by the extra RAM memory generally become more expensive relative to using methods of re-spinning new ASICs to debug and test ASICs.
Accordingly, what is needed is an improved technique that permits testing for the correct operation instructions within a ROM memory of a microcontroller that does not require a re-spin of an ASIC to modify the instructions and which is cost effective in terms of use of silicon real estate. The present invention addresses such a need.